1. Field of the Invention
This invention relates to insulated gate field effect transistors and methods of producing the same and, more particularly, to insulated gate field effect transistors in which a low impurity concentration layer is disposed in the drain region, whereby the feedback capacitance between the gate and drain is lowered and the transconductance is increased, and thus improved high frequency characteristics are obtained.
2. Description of the Prior Art
To improve the high frequency characteristic of metal insulator semiconductor field effect transistor (hereinafter briefly referred to as MIS-FET) in the prior art, it has been known to be effective if the channel length of the gate region (channel region) located between the source and drain regions is made as short as possible and the capacitance between the gate and drain (or source) is reduced.
To realize this idea, a method of producing MIS-FET for high frequency applications was proposed in U.S. Pat. No. 3,472,212 and in U.S. Pat. No. 3,596,347. According to this method, a gate electrode is disposed on one surface of a semiconductor substrate by way of an insulation layer, and source and drain regions are formed on the substrate by ion implantation using the gate electrode as a mask. In this MIS-FET, the channel length depends on the gate electrode width. In other words, the channel length can be reduced to the extent where photo-etching is applicable for the formation of the gate electrode. The source and drain regions can be formed without increasing the capacitance between the gate and drain for source, contrary to the method of forming the source and drain regions by impurity diffusion, wherein the source and drain regions are extended to the region beneath the gate electrode and the gate electrode is superposed on the source or drain region to increase the capacitance therebetween. In the MIS-FET with a reduced channel length, however, there exists the tendency of the punch-through phenomenon between the source and drain, due to expansion of the depletion layer in the channel region with an increase in the bias across the drain and source. Furthermore, the transconductance is varied widely by a change in the bias voltage.
To solve the problem of punch-through, some improved MIS-FETs in which a region of low impurity concentration is disposed in the drain region have been proposed heretofore. One of these MIS-FETs utilizes a double diffusion technique wherein an impurity for forming the gate region and an impurity for forming the source region are thermally diffused in succession into a semiconductor substrate (to become the drain region) of low impurity concentration, whereby the source, gate and drain regions are formed along the vertical direction from the surface to the base of the substrate. Another MIS-FET is such that the gate region whose conductivity type is reverse or opposite to that of the substrate is formed on the surface of a semiconductor substrate of low impurity concentration by an impurity diffusion process, and a layer of high impurity concentration whose conductivity type is the same as that of the substrate is disposed on both sides of the gate region on the surface of the substrate, whereby the drain and source regions are formed.
In the former MIS-FET, the channel length (the gate region width) can be reduced because the MIS-FET is formed by double diffusion. However, it is difficult to provide a gate electrode lead; rarely, part of the surface of the substrate is etched down to the gate diffusion layer to expose the gate region, the hollow part formed by the etching is covered with a thin insulation film and the hollow is filled with a sufficiently thick gate electrode metal layer. In such structure, it is inevitable that the source region and gate electrode are superposed on each other and, as a result, the source gate capacitance is increased.
In the latter MIS-FET, a narrow gate region (short channel length) can hardly be realized because the gate region is formed by impurity diffusion. Furthermore, the electrical isolation between the source and drain is reduced because the source and drain regions are linked with each other by way of the low impurity concentration substrate whose conductivity type is the same as those of the source and drain regions.
To obtain a low output capacitance and a relatively close spacing of source and drain regions, a further MIS-FET has been proposed in British Pat. No. 1,153,428. This MIS-FET has the drain region comprising two semiconductor regions, one of which is surrounded by the other having a lower impurity concentration than that of said one region. However, in this MIS-FET, a gate electrode extends over p-n junctions between the respective source and drain regions, and hence a gate-source feedback capacitance becomes large. For this large capacitance, at high operating frequencies, the impedance of capacitive coupling will be so low as to be a substantial short circuit, so that when an input signal is applied, substantially no useful output signal is obtained.
Referring first to FIG. 5, there is shown a structure of one MIS-FET considered from MIS-FETs described in U.S. Pat. No. 3,596,347 and British Pat. 1,153,428.
This MIS-FET comprises as n-type silicon substrate 50, a p-type semiconductor region 51 which acts as a main source, disposed in the substrate 50, a p-type semiconductor region 52 which acts as a main drain, disposed in another portion of the substrate 50, an insulating layer 53 disposed on the surface of the substrate 50 between the source and drain regions 51 and 52, a p-type semiconductor region 54 having a lower impurity concentration than that of the main source region 51, which acts as a sub-source, disposed in the substrate 50 so that one end thereof contacts to the main source region 51, a p-type semiconductor region 55 having a lower impurity concentration than that of the main drain region 52, which acts as a sub-drain, disposed in the substrate 50 so that one end thereof contacts to the main drain region 52, a gate electrode 56 disposed on the insulating layer 53 at a portion corresponding to a portion of the substrate 50 between the sub-source and drain regions, and source and drain electrodes 57 and 58 contacted to the main source and main drain regions, respectively.
With this type of structure, a resistance R.sub.S between the source region and the gate electrode becomes large. When the resistance R.sub.S becomes large, the transconductance g.sub.m.sbsb.e.sbsb.f.sbsb.f decreases, as illustrated below, as compared with a device which does not have a resistance R.sub.S. Namely, g.sub.m.sbsb.e.sbsb.f.sbsb.f = g.sub.m /(1 + g.sub.m R.sub.S).
Generally, since the drain current I.sub.D and the cut-off frequency f.sub.c of the device are established as follows: EQU I.sub.D = 1/2 g.sub.m (V.sub.G - V.sub.T),
and EQU f.sub.c = g.sub.m /2.pi.C,
where V.sub.T is the threshold voltage of the device,
V.sub.G is the gate voltage, and
C is the capacitance, when the trans-conductance is decreased, the drain current I.sub.D and the cut-off frequency of the device decrease, so that a high output gain and a high frequency response cannot be obtained.
For purposes of further illustration, a concrete determination of the trans-conductance g.sub.m.sbsb.e.sbsb.f.sbsb.f of the device will be calculated below.
The sheet resistivity .rho..sub.S of the n-region is about 10.sup.20 K.OMEGA./ for the device having a high breakdown voltage characteristic and a low capacitance characteristic. As a result, the resistance R.sub.S of the low impurity concentration region 1 is determined as follows: EQU R.sub.S = .rho..sub.S (W.sub.R /L.sub.R),
wherein L.sub.R and W.sub.R are the length and the width of the low impurity concentration region 1, respectively.
Now, for the transconductance g.sub.m being established by EQU g.sub.m = (10 to 20) .times. 10.sup..sup.-6 .times. (V.sub.G - V.sub.T) (W.sub.C /L.sub.C)
wherein L.sub.C and W.sub.C are the length and width of the channel respectively, and the widths W.sub.R and W.sub.C are equal to each other, then, when the lengths L.sub.R and L.sub.C are nearly equal to each other, and (V.sub.G - V.sub.T) is equal to 10V, the product R.sub.S .sup.. g.sub.m = 1 to 4 and hence, the effective transconductance g.sub.m.sbsb.e.sbsb.f.sbsb.f decreases to a value of 50 to 20% of g.sub.m.
Since the drain current and the cut-off frequency of the device are proportional to its transconductance, for a low impurity concentration region being disposed between the source and gate electrode, the characteristics of the device deteriorate.
The present invention eliminates above-mentioned defects, in other words, the present invention provides superior electronic characteristics.
A general object of this invention is to provide a MIS-FET in which the channel length is short and the drain region comprises a region whose impurity concentration is low, and to provide a method of producing such MIS-FET.
Briefly, in connection with a semiconductor device which comprises a semiconductor substrate, a source region, a drain region and a gate region, wherein the source and drain regions whose conductivity types are reverse or opposite to that of the substrate, are formed on the surface of the substrate by way of the gate region whose conductivity type is the same as that of the substrate, the MIS-FET of this invention is characterized in that the drain region comprises a region having a low impurity concentration, and a region having a high concentration of impurity with the same conductivity type as that of the substrate is disposed in the low impurity concentration region. The method of producing such a MIS-FET according to this invention is characterized in that an insulated gate electrode is disposed on the surface of the semiconductor substrate, this electrode is used as a mask to implant thereinto ions of an impurity whose conductivity type is reverse to that of the substrate, thereby forming a low impurity concentration region in the area corresponding to at least the drain region on the surface of the substrate and also forming a high impurity concentration region whose conductivity type is reverse to that of the substrate in the area corresponding to the low impurity concentration region and the source region.
According to this invention, the purpose of disposing a low impurity concentration region in the drain region is to keep the depletion layer from being extended into the gate region and to prevent the formation of large gate drain feedback capacitance even if the gate electrode is superposed on the low impurity concentration region.
In the prior art, there exist difficulties in forming a low concentration diffusion layer on the surface of a semiconductor substrate. In contrast thereto, the invention provides a solution to this problem. Namely, a low concentration impurity diffusion layer is formed on the drain region by utilizing ion implantation techniques. In the method of forming an ion implantation region in a semiconductor substrate, the depth and concentration of the implantation region can be accurately controlled by suitably determining the ion energy, the ion current density, the implanting time, etc.
The concept of "low impurity concentration" used according to this invention denotes a low impurity concentration relative to the concentration of an impurity added thereto by the usual impurity thermal diffusion technique.
Furthermore, since usually the impurity concentration of the substrate of a MIS-FET is not too high (for example, 5.0 .times. 10.sup.15 /cm.sup.3), the gate drain feedback capacitance is not appreciably large. This helps realize an operably ideal circuit design.
The invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings.